In May 8, 2012, promote the φ<₩↕use of TSV ( TSV ) 3D lamin εated to a new generation of DRAM " Hybδ×rid Memory Cube ( HMC ) Hybrid Memory Cub₽✔♥e Consortium " popularity ( HMCC π★₽) announced that the United States, software gγ≥∑iant Microsoft has joined the association±♠∑.

　　HMC is the three-dimensional structur♠ ≈e, the logic chip along the ve​α←←rtical direction superposi♣↓tion of multiple DRAM chips, and then th♠₽ rough the TSV connection wiring tec± ✘♠hnology. HMC 's biggest characteristic∑™© is compared with existing D≠®RAM, performance can be greatly i↔≠§mproved. The reasons there are two, one σ  is between chips from semiconductor p∏★&ackage wiring distance on a b≥£←oard on the traditional methods of " cm " unδ$∑↔its are substantially reduced to do∏≈≈σzens ofμ m～ 1mm; two is on a chip to form ¥¶φ×1000 to tens of thousands of TSVφ→←, realize the multipoint connection chip.

　　Microsoft 's accession to the HMC♣←∞C, because we are considering how to correspondin∑σ✔g is likely to become a personal cα¥☆omputer and a computer to improving tφ→he performance of " memory bottle↕★γ∞neck " problem. Memory bottleneck refers to as>​ the microprocessor performance through mul§€π♠tiple nucleation and constantlyε§←★ improve, the architecture of the DRAM performanπ≈♥×ce will not be able to meet the need λ×&of processor. If do not solve this problem, can o αccur even if the computer new produc"αt, the actual performance is also not appr‌©™opriate promotion situation. Co★₽mpared with it, if the TSV based on the app₽α<₽lication of HMC in computer main memory, the ® ∑₩data transmission speed can be increased to t≠‍δhe current DRAM is about 15 t∏ imes, therefore, is not just a giant Microsoβ±☆ft, American companies such as Int★↔‍el are also active in research using HMC.

　　In fact, plans to use TSV not only foπ<r HMC and other DRAM produ♥Ωcts. According to the semiconductor€♦ manufacturers plan, in the next few φ>years, borne from electronic equipment input ₹"&$function of the CMOS sensor t‍α​©o the responsible for the oλ±perations of FPGA and multi core processor, and Ωδαin charge of product storage of DRAM׶ and NAND flash will have to i ±mport TSV. If the plan goes ahead, TSV™© will assume the input, operation©‌ ♠, storage and other electronic ✔δ€>equipment main function.